Buried parts simplify fine geometry electronic packaging, interconnect, & assembly

The evolutionary developments in integrated circuits predicted by Moore´s Law apply steady pressure on packaging, interconnect, and assembly to deliver finer geometry. As conventional technology, such as subtractive PWB patterning and chips-last assembly, approaches performance, cost and yield barriers, innovative approaches become competitive in spite of potential infrastructure disruptions. In particular, the notion of embedding traces and devices within the interconnect substrate has emerged as an attractive yet unconventional means to achieving fine geometry systems. Innovative concepts in embedded technology lead the way to miniaturization, cost reduction and performance enhancement. For example, Imprint Patterning (IP) buries traces to enable padless designs and maskless soldering with a variation of the stamper technology employed in CD and DVD production. Remarkably, IP delivers these benefits at higher yield and lower cost than conventional board processes. Similarly, Chips-First assembly enables superior electrical performance and thermal management by embedding devices and adding interconnect afterwards. Inherently scalable, Chips-First assembly replaces wire-bonds and solder bumps with direct metallurgical connections to the chip. Finally, Capillary Chip Connection (C3) allows fine pitch joining with reduced electrical parasitics by replacing solder balls with minute solder menisci. This paper reviews these three embedded approaches to fine geometry and assesses their outlook and opportunities with particular attention to potential infrastructure disruptions and business model concerns.