Title :
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies
Author :
Nunez, Juan ; Avedillo, Maria J. ; Quintana, Jose M.
Author_Institution :
Inst. de Microelectron. de Sevilla-CSIC, Univ. de Sevilla, Sevilla, Spain
Abstract :
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high throughput. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and the Carry-Merge chain of a Kogge-Stone adder is designed as an application example.
Keywords :
delay circuits; integrated circuit noise; logic design; network topology; pipeline processing; Carry-Merge chain; DSM technologies; Kogge-Stone adder; commercial applications; competitive delay-noise tradeoffs; dynamic gate topology; dynamic logic; fine grained pipelines; fine-grained pipeline; frequency targets; function-independent delays; functional limitation; gate static output stage; high performance functional units; inverting functionalities; labor-intensive design; logic design; noise susceptibility; superpipelines; Clocks; Delays; Logic gates; Noise; Pipeline processing; Topology; Transistors; Delay-noise trade-off; dynamic logic; fine grained pipelining;
Conference_Titel :
Digital System Design (DSD), 2013 Euromicro Conference on
Conference_Location :
Los Alamitos, CA
DOI :
10.1109/DSD.2013.141