A low power register scheduling and allocation algorithm for multiple voltage

The low power register scheduling and allocation algorithm is concerned with minimum switching activity and low power multiple voltages. The proposed algorithm executes low power scheduling to reduce switching activity using a shut down technique by the creation of a data flow graph (DFG) from the VHDL description. Also, the low power register allocation algorithm determines the minimum register after the life time analysis of all variables. It minimizes the switching activity using a graph coloring technique for low power consumption. Finally, the total power is reduced by using the low power multiple voltage. The proposed algorithm proves the effect through various filter benchmarks to adopt a low power register scheduling and allocation algorithm considering resource constraint at multiple voltage