Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures

We introduce a power optimization technique for suppression countermeasures against Power Analysis attacks that can potentially be applied to any type of crypto-system implemented as a synchronous digital system. Since the power consumption of systems protected by suppression countermeasures is proportional to current peaks, we propose a simple transformation to move some of the switching activity of the crypto-system from the rising edge to the falling edge of the clock, so that current peaks are reduced. The transformation is easy to apply, requires only standard cell logic gates, has a low area overhead but can reduce the maximal working frequency of a system by at most a factor 2. We prove our method on an ASIC implementation of the Grain-80 stream cipher using SPICE-level simulation, obtaining 50% power savings compared to the non-optimized suppression countermeasure.