DocumentCode
3480184
Title
MAX EPLD Family: PAL Speed to FPGA Density
Author
Jorgens, Bruce
Author_Institution
Altera Corporation
fYear
1991
fDate
16-18 April 1991
Firstpage
350
Lastpage
355
Keywords
Clocks; Feeds; Field programmable gate arrays; Flip-flops; Logic arrays; Logic devices; Macrocell networks; Packaging; Plastics; Programmable logic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Electro International, 1991
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ELECTR.1991.718235
Filename
718235
Link To Document