3480247

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

Nambu, H. ; Kanetani, K. ; Idei, Y. ; Masuda, T. ; Higeta, K. ; Ohayashi, M. ; Usami, M. ; Yamaguchi, K. ; Kikuchi, T. ; Ikeda, T. ; Ohhata, K. ; Kusunoki, T. ; Homma, N.

Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan

1994

9-11 June 1994

109

110

BiCMOS integrated circuits; CMOS memory circuits; Decoding; Delay effects; Laboratories; Power dissipation; Pulse width modulation inverters; Random access memory; Read-write memory; Space vector pulse width modulation;

English

ieee

VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on

Honolulu, HI, USA

0-7803-1918-4

conf

10.1109/VLSIC.1994.586240

586240