DocumentCode
3480340
Title
Simulation and SAT Based ATPG for Compressed Test Generation
Author
Balcarek, Jiri ; Fier, Petr ; Schmidt, J.
Author_Institution
Dept. of Digital Design, Czech Tech. Univ. in Prague, Prague, Czech Republic
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
445
Lastpage
452
Abstract
This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.
Keywords
automatic test pattern generation; computability; RESPIN architecture; SAT based ATPG; compressed test generation; interconnected embedded cores; satisfiability-based techniques; symbolic simulation; Algorithm design and analysis; Automatic test pattern generation; Benchmark testing; Circuit faults; Computer architecture; Integrated circuit modeling; Vectors; ATPG; RESPIN; embedded cores; satisfiability; symbolic simulation; test compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2013 Euromicro Conference on
Conference_Location
Los Alamitos, CA
Type
conf
DOI
10.1109/DSD.2013.56
Filename
6628311
Link To Document