A 622-MHz CMOS phase-locked loop with precharge-type phase frequency detector

A new approach to implement high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec and is less than a half of conventional detector. A bias generator with complementary input stage is also developed to enhance the dynamic range of the VCO under low supply voltage. A fully CMOS phase-locked loop (PLL) was designed using 0.5-μm technology. By virtue of this simple fast detector and bias generator, 622-MHz stable operation was achieved by simulation.