• DocumentCode
    3480490
  • Title

    Voltage Spikes on the Substrate to Obtain Timing Faults

  • Author

    Tobich, Karim ; Maurine, P. ; Liardet, P.-Y. ; Lisart, M. ; Ordas, T.

  • Author_Institution
    LIRMM, Univ. Montpellier II, Montpellier, France
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    483
  • Lastpage
    486
  • Abstract
    Fault attacks are widely deployed against secure devices by hardware evaluation centers. While the least expensive fault injection techniques, like clock or voltage glitches, are well taken into account in secure devices by dedicated hardware counter-measures, more advanced techniques, such as light based attacks, require huge investments. This paper presents a new way to induce faults at a moderate cost that may defeat already in place hardware counter-measures. To demonstrate its effectiveness we applied this technique on an ASIC component. For this demonstration, fault exploitation is operated using the classic Bell core attack applied on a modular exponentiation supported by a modular arithmetic co-processor.
  • Keywords
    application specific integrated circuits; electrical faults; power supply quality; substrates; ASIC component; classic Bellcore attack; modular arithmetic co-processor; substrate; timing faults; voltage spikes; Circuit faults; Clocks; Integrated circuits; Random access memory; Substrates; Timing; Transient analysis; Chinese Remainder Theorem; Electromagnetic Attacks; Fault Attacks; Forward Body Biasing Injection; RSA;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design (DSD), 2013 Euromicro Conference on
  • Conference_Location
    Los Alamitos, CA
  • Type

    conf

  • DOI
    10.1109/DSD.2013.146
  • Filename
    6628318