Title :
High-speed CORDIC architecture based on redundant sum formation and overlapped σ-selection
Author :
Choi, Jae Hun ; Kwak, Jae-Hyuck ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper presents an architecture for accelerating CORDIC vectoring mode operations. The processing is sped up by overlapping redundant sum formation and selection of rotation direction. We analyze the latency time and area, and compare them with a conventional CORDIC implementation. The results show that the proposed scheme reduces not only the the latency but also the overall computation time. Thus, it achieves higher throughput in pipelining
Keywords :
carry logic; circuit optimisation; high-speed integrated circuits; logic design; pipeline arithmetic; redundant number systems; CORDIC vectoring mode operations; high-speed CORDIC architecture; latency time; overlapped sigma-selection; pipelining; redundant sum formation; rotation direction; Added delay; Circuits; Delay effects; Delay estimation; Equations; Hardware; Logic; Performance analysis; Throughput; Timing;
Conference_Titel :
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-0406-X
DOI :
10.1109/ICCD.1999.808388
