Accurate power estimation for CMOS circuits

In this paper, we develop a new analytical equation model for power estimation because of its properties of low runtime, less storage, and high accuracy for Very Deep Sub-micron Semiconductor (VDSM) CMOS gates. Our analytical equation model consists of (i) a physical α-power law MOSFET model of simple mathematical form and high degree of accuracy for the I/V characteristics for the specific pMOS and nMOS, (ii) analysis and future trend of short-circuit power model with inclusion of short-channel effects through a velocity saturation index (α) of the α-power law MOSFET model and more accuracy than the previously published formulas for the specific CMOS gate, and (iii) equation model from BSIM3 manual. We demonstrate our analytical model on some benchmark gates and show the error of 2.72% in average. In addition, we simulate our equation model in machine SUNW, Ultra-5-10 aid it only takes 2-4 seconds. Furthermore, only a few storages are needed for the Netlist information instead of thousands of look-up tables for transistors and logic cells