Design and implementation of a parallel weighted random pattern and logic built in self test algorithm

Author

Chang, Paul ; Keller, Brion ; Paliwal, Sarala

Author_Institution

IBM Server Div., Endicott, NY, USA

fYear

1999

fDate

1999

Firstpage

175

Lastpage

180

Abstract

An increase in chip densities has led to a significant increase in test generation and fault simulation times. Analysis of various test methodologies has shown that logic built in self test (LBIST) and weighted random pattern test (WRPT) are a significant portion of the execution time. Several parallel algorithms have been proposed to reduce run times for ATPG. This paper describes, for the first time, the parallelization of the LBIST and WRPT algorithms. Results on industrial circuits that range in size from 300,000 gates to about 1 million gates are presented. Previous works have published results on parallelization of deterministic testing and simulation for smaller circuits

Keywords

automatic test pattern generation; built-in self test; circuit simulation; fault simulation; logic testing; parallel algorithms; ATPG; execution time; fault simulation times; industrial circuits; logic built in self test algorithm; parallel algorithms; parallel weighted random pattern test algorithm; parallelization; run time reduction; test generation time; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Clocks; Logic design; Logic testing; Pattern analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 1999. (ICCD '99) International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0406-X

Type

conf

DOI

10.1109/ICCD.1999.808423

Filename

808423