• DocumentCode
    3480817
  • Title

    A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems

  • Author

    Cervero, T. ; Dondo, J. ; Gomez, Ariel ; Pena, X. ; Lopez, Sebastian ; Rincon, F. ; Sarmiento, R. ; Lopez, J.C.

  • Author_Institution
    Inst. Univ. de Microelectron. Aplic., Univ. of Las Palmas Gran Canaria, Las Palmas Gran Canaria, Spain
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    633
  • Lastpage
    640
  • Abstract
    FPGA-based embedded systems are gaining relevance for implementing a wide range of applications. Part of their success is due to their balanced compromise between performance and flexibility, but also because of their capability for exploiting the dynamic reconfiguration. However, the costly reconfiguration process and the lack of management support have prevented a broader use of the FPGAs. In order to contribute to solve these issues, in this paper we propose a software/hardware dynamic resource management system that combines scheduling and placement tasks, providing a complete management flow for supporting dynamically reconfigurable hardware designs. One of the advantages of the proposed model is the capability for running its scheduling and placement tasks in different nodes, as part of a distributed network. The results of our experiments demonstrate that our placement policy, specially designed for reconfigurable systems, achieves good results, in terms of reusability and performance, compared to other management approaches.
  • Keywords
    distributed processing; embedded systems; field programmable gate arrays; reconfigurable architectures; resource allocation; scheduling; distributed network; dynamically reconfigurable FPGA-based embedded systems; placement task; reconfigurable systems; reconfiguration process; resource manager; reusability; scheduling task; software-hardware dynamic resource management system; Dynamic scheduling; Engines; Field programmable gate arrays; Hardware; Object recognition; Software; Dynamic reconfiguration; FPGA; hierarchical reconfigurable region; reconfiguration engine; scalable design; scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design (DSD), 2013 Euromicro Conference on
  • Conference_Location
    Los Alamitos, CA
  • Type

    conf

  • DOI
    10.1109/DSD.2013.75
  • Filename
    6628336