DocumentCode
348107
Title
A tool portfolio planning methodology for semiconductor wafer fabs
Author
You, R.-C. ; Weng, C.-R. ; Chou, Y.-C. ; Wu, H. Henry ; Lu, L.-C.
Author_Institution
Nat. Taiwan Univ., Taipei, Taiwan
fYear
1999
fDate
1999
Firstpage
11
Lastpage
14
Abstract
Tool portfolio planning is an ongoing task in wafer fabs, as process, tool and product technologies evolve constantly and production in most times undergoes ramping-up. Precision and soundness of portfolio planning are therefore a crucial capability of wafer fab operation. This paper describes a tool portfolio planning methodology developed in a joint university-industry project. An improved static capacity model is first presented, in which an empirical formula is used to estimate the efficiency of batch tools. A portfolio planning procedure based on static capacity estimation and queueing analysis is next described. This procedure enables the portfolio solution space to be explored easily and has demonstrated superior performance in preliminary benchmarking in an industry case study
Keywords
batch processing (industrial); integrated circuit manufacture; queueing theory; semiconductor process modelling; strategic planning; batch tools; joint university-industry project; portfolio planning procedure; preliminary benchmarking; queueing analysis; semiconductor wafer fabs; static capacity model; tool portfolio planning methodology; Capacity planning; Delay estimation; Paper technology; Portfolios; Process planning; Production planning; Semiconductor device modeling; Space exploration; Technology planning; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
0-7803-5403-6
Type
conf
DOI
10.1109/ISSM.1999.808726
Filename
808726
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