DocumentCode
348113
Title
Reduction of probe to pad contact resistance: technology development targeted for cost effectiveness Pentium II(R) processors testing
Author
Roggei, A. ; Seshan, Krishna
Author_Institution
Intel, Qiryut Gat, Israel
fYear
1999
fDate
1999
Firstpage
217
Lastpage
219
Abstract
This paper presents work done during the technology development phase in Intel. The goal was to achieve capability and cost effectiveness for high volume manufacturing of Pentium II(R) processors. The work addressed problems in wafer testing of high-speed microprocessors. These problems stem from the phenomenon of resistance increase between probes and pads during the probing process (contact resistance). This work eliminated the root cause of probing process problems using an innovative approach of Fab process improvement. The result was a robust probing process on time for introduction of the product line. Harnessing technology development for high manufacturability saved many millions of dollars during high volume production of WireBond tight pitch, high-speed microprocessors
Keywords
contact resistance; cost-benefit analysis; integrated circuit economics; integrated circuit testing; lead bonding; microprocessor chips; probes; production testing; surface cleaning; Pentium II processor testing; WireBond tight pitch; cleaning process; cost effectiveness; cost of ownership; high volume manufacturing; high-speed microprocessors; pad surface; probe to pad contact resistance reduction; probing process problems; sort testing friendly fab process; technology development phase; wafer testing; Atherosclerosis; Chromium; Cleaning; Contact resistance; Costs; Fabrication; Manufacturing processes; Microprocessors; Probes; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
0-7803-5403-6
Type
conf
DOI
10.1109/ISSM.1999.808775
Filename
808775
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