A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors

The trend for multicore processor architectures indicates an ongoing increase in computing cores per chip. The resulting challenges demand for a revision of the applicability of existing hardware operating systems. We propose a scalable best-effort task scheduler implemented in hardware, which services a homogeneous multiprocessor architecture. The hardware scheduler realizes a master/slave system to maximize available parallelism. Experimental results show the scalability of the hardware scheduler in terms of performance, area and power. A design pattern to generate a hierarchical communication architecture for task management is prospected.