DocumentCode
3481159
Title
Exploiting Petri net graph to model the FSM of modulo-P counter
Author
Jih-Fu Tu
Author_Institution
Dept. of Electron. Eng., St. John´´s & St. Mary´´s Inst. of Technol., Taipei
Volume
2
fYear
2004
fDate
1-3 Dec. 2004
Firstpage
1090
Lastpage
1094
Abstract
Traditionally, the basic abstract of a system is described by the general static machine. If we want to model the transactions of the discrete-event system (DES), the finite state machine model does not clearly and evidently to illustrate the state transition. For illustrating and modeling a high-performance state transition system, we can use the Petri nets (PNs) graph to replace the concepts of traditional finite state machine (FSM). In this paper, we issue some novel kinds of elements of the Petri net to replace the FSM, furthermore, to illustrate the state transition. In order to make the focal points stand, we give an example, in which we use the Petri net graph to illustrate the combination logic control circuit of Modulo-p counter, to prove our assumption
Keywords
Petri nets; discrete event systems; finite state machines; logic circuits; FSM; Modulo-p counter; Petri net graph; combination logic control circuit; discrete-event system; finite state machine model; state transition system; Automata; Circuit simulation; Counting circuits; Discrete event systems; Hardware; Information processing; Logic circuits; Petri nets; Process design; Software algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Cybernetics and Intelligent Systems, 2004 IEEE Conference on
Conference_Location
Singapore
Print_ISBN
0-7803-8643-4
Type
conf
DOI
10.1109/ICCIS.2004.1460741
Filename
1460741
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