Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems

Advanced high-speed source-synchronous systems such as GDDR5 use multiple source-synchronous clocks to increase memory bandwidth. Therefore, well-defined phase relationships among multiple clocks are required to perform correct read/write operations. A GDDR5 system solves this problem by adaptive clock synchronization training. For such multiple clocks synchronization training at controller side this paper proposes two simplified architectures based on: a) Unit-delay incrementer, b) PI (Phase-Interpolator) based PLL (Phase-Locked Loop). Experiments show that the proposed unit-delay architecture consumes only 0.89 mW power and 100 (μm)² area in 65nm which is 16.8 times less power and 35 times less area than other works while power and area consumed in the PI-based PLL architecture depends upon the complexity of the PI itself.