DocumentCode
3481348
Title
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks
Author
Souto Vieites, Angela ; Osorio, Roberto R.
Author_Institution
Dept. of Electron. & Syst., Univ. of A Coruna, Coruna, Spain
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
799
Lastpage
802
Abstract
In this work, a new architecture for loss less data compression and decompression is integrated within an Ethernet switch using the NetFPGA open platform. The aim is compressing data packets in a block-based storage network. Data packets are compressed when written to the target disk and decompressed when read by the initiator. ATA-over-Ethernet (AoE) has been chosen as it is an efficient and relatively simple technology that does not rely on IP. The ultimate goal is achieving a better use of the available network bandwidth with the target and a possible reduction in power consumption. The use case of application-level check pointing in supercomputing is presented, for which compression ratios are given, and the efficiency of the proposed scheme is then discussed.
Keywords
checkpointing; data compression; local area networks; storage area networks; ATA-over-Ethernet storage networks; AoE; Ethernet switch; NetFPGA open platform; application-level check pointing; block-based storage network; data decompression; loss less data compression system; power consumption; supercomputing; switch-level; Bandwidth; Checkpointing; Computer architecture; Data compression; IP networks; Storage area networks; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2013 Euromicro Conference on
Conference_Location
Los Alamitos, CA
Type
conf
DOI
10.1109/DSD.2013.122
Filename
6628360
Link To Document