SDLDS—System for Digital Logic Design and Simulation

This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and laboratory work, and by teachers to automate the assessment and verification of students´ work. The system allows users to design and simulate a switching circuit. It also collects data on all student activities and transfers these to the school´s information system. Finally, the paper gives figures demonstrating the overall benefits of the system.