Title :
A processor network without interconnection path
Author :
Stefan, Denisa ; Stefan, Gheorghe
Author_Institution :
Waferscale Integration Inc., Fremont, CA, USA
Abstract :
In the current silicon technologies the wire connections become more and more important. They will waste time, energy and maybe area more than the gates. Beyond the technological solutions for this problem, architectural solutions are welcome. This paper discusses a solution which completely avoids the interconnections in a 4-processor network. More, the four processors share many structural resources, thus minimizing the size of the entire structure. The pipeline penalties are completely avoided in the proposed structure. The machine we describe is an environment for interleaved multi-threaded executions
Keywords :
integrated circuit interconnections; integrated circuit modelling; 4-processor network; architectural solutions; interconnection path; interleaved multi-threaded executions; pipeline penalties; processor network; wire connections; Algorithm design and analysis; Circuit testing; Clocks; Counting circuits; Frequency; Logic testing; Pipelines; Reduced instruction set computing; Registers; Yarn;
Conference_Titel :
Semiconductor Conference, 1999. CAS '99 Proceedings. 1999 International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-5139-8
DOI :
10.1109/SMICND.1999.810524
