Electric-thermo-mechanical analysis of TSV under high current stressing

As one of the most promising technologies for future 3D IC integration, through silicon via (TSV) has gained wide attention. But its reliability issues are a great concern. This paper presents an analysis of the electric-thermo-mechanical reliability of TSV structures under high current stressing using finite element method (FEM). Based on the comprehensive analysis of the temperature, current density and stress distribution, we suggest that the interface locations between TSV and metal levels where the cross area changes as current flows in or out of TSV should be carefully considered. These locations are with higher temperature, current density and stress concentration, which may lead to the failure of TSV. Furthermore, we also investigate the effects of three geometrical parameters, namely, SiO₂ oxide layer thickness, the diameter and the length of TSV on its electric-thermo-mechanical reliability. Properly decreasing the SiO₂ layer thickness can improve its thermo-mechanical reliability, but the more severe current crowding can result in the electromigration at the interface locations. To ensure the reliability, TSV with larger diameter and shorter length are also recommended.