Analysis of thermal cycling testing for a 3D integrated package with inter-chip microbumps

While in the past, the silicon, package and system could be designed sequentially, at silicon nodes less than 40nm, the interconnects between the chip, package and system are becoming the limiting factor in performance and reliability. To better capture the warpage and fatigue, an improved slice model with much more detail about the bumps, microbumps, underfill, fillet etc., was simulated. The silicon interposer with array-type Through-Silicon Vias (TSVs) can be regarded as a composite material. Hence, the effective modulus and Coefficient of Thermal Expansion (CTE) of the TSV interposer were first independently derived. Multi-point Constraints (MPCs) and contact elements were employed in the model to capture the interactions accurately. Submodeling, an alternative solution for computation time-saving was also evaluated. Finally, a series of analyses were run to obtain the variation trends for the accumulated creep Strain Energy Density (SEND) vs. different parameters.