Closed-form expression for capacitance of tapered through-silicon-vias considering MOS effect

Author

Fengjuan Wang ; Yintang Yang ; Zhangming Zhu ; Xiaoxian Liu ; Yan Zhang

Author_Institution

Sch. of Microelectron., Xidian Univ., Xi´an, China

fYear

2013

fDate

11-14 Aug. 2013

Firstpage

1250

Lastpage

1254

Abstract

In this paper, closed-form expression of the parasitic capacitance of the tapered Through-Silicon Via (TSV) is proposed, which also cover the cylindrical TSV when the slop wall angle is 90°. The comparison between the results of Ansoft Q3D verification and Matlab calculation are made. It shows that the root mean square error is less than 6.10%, over a wide range of the bottom radius and the height of tapered TSV, and the oxide thickness, therefore, the expression presented proves to be accurate.

Keywords

MOS integrated circuits; capacitance; integrated circuit interconnections; integrated circuit reliability; three-dimensional integrated circuits; MOS effect; Matlab calculation; closed form expression; cylindrical TSV; oxide thickness; parasitic capacitance; root mean square error; tapered TSV; tapered through silicon vias; Capacitance; Closed-form solutions; Integrated circuit modeling; MATLAB; Silicon; Three-dimensional displays; Through-silicon vias; MOS Effect; Parasitic Capacitance; Poisson´s Equation; Tapered TSV;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2013 14th International Conference on

Conference_Location

Dalian

Type

conf

DOI

10.1109/ICEPT.2013.6756684

Filename

6756684