SIPOS-passivation for high voltage power devices with planar junction termination

Author

Stockmeier, T. ; Lilja, K.

Author_Institution

ABB Asea Brown Boveri Corp. Res., Baden, Switzerland

fYear

1991

fDate

22-24 Apr 1991

Firstpage

145

Lastpage

148

Abstract

Power diodes have been fabricated with a planar junction termination suitable for breakdown voltages up to 6.2 kV. The devices were passivated with a double layer of SIPOS (semi-insulating polycrystalline silicon) and silicon nitride, directly deposited on the silicon surface. The influence of the SIPOS layer on the current distribution in the device while in the blocking state was investigated by numerical simulation and experimentally. It was found that SIPOS acts simply as a resistive layer and that the portion of the reverse current which flows through the passivation layer is given by the balance of the resistances of the space charge region and the SIPOS layer. Therefore, if the resistance of the SIPOS layer is adjusted carefully (by its oxygen content and its lateral and vertical dimensions), high voltage diodes can be passivated with a semi-insulating material, and an excellent blocking behavior can be achieved

Keywords

electric breakdown of solids; passivation; power electronics; semiconductor diodes; space-charge-limited conduction; SIPOS; Si; Si-Si₃N₄; blocking state; breakdown voltages; current distribution; high voltage diodes; high voltage power devices; planar junction termination; resistive layer; semi-insulating polycrystalline silicon; space charge region; Conductivity; Current distribution; Diodes; Insulation; Low voltage; Numerical simulation; Passivation; Semiconductor materials; Silicon; Space charge;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1991. ISPSD '91., Proceedings of the 3rd International Symposium on

Conference_Location

Baltimore, MD

ISSN

1063-6854

Print_ISBN

0-7803-0009-2

Type

conf

DOI

10.1109/ISPSD.1991.146086

Filename

146086