Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform

Author

Sukegawa, K. ; Yamamoto, Takayuki ; Kudo, Hiroyuki ; Kubo, T. ; Sukegawa, Takashi ; Ehara, H. ; Ochmizu, H. ; Fukuda, Motohisa ; Mizushima, Y. ; Shimoda, Y. ; Tajima, Michio ; Oryoji, M. ; Nakata, Y. ; Watatani, H. ; Sakai, Hiroki ; Asneil, A. ; Sakai, Sh

Author_Institution

Fujitsu Lab. Ltd., Tokyo

fYear

2007

fDate

12-14 June 2007

Firstpage

174

Lastpage

175

Abstract

We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V_d=1.2 V are 0.54 mA/um at I_off=40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.

Keywords

MOSFET; lead bonding; superconducting interconnections; LSTP platform; annealing process; full-porous low-k interconnect; low-leakage/ low-cost transistor; mechanical toughness; nMOS; pMOS; size 45 nm; stress migration; wire bonding; Annealing; Bonding; Delay; Dielectrics; Leakage current; MOS devices; Plasma chemistry; Thermal stresses; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339681

Filename

4339681