DocumentCode
3484335
Title
High-level timing analysis using constraint logic programming and interval arithmetic
Author
Girodias, Pierre ; Cerny, Eduard
Author_Institution
Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
Volume
2
fYear
1995
fDate
5-8 Sep 1995
Firstpage
636
Abstract
This paper addresses the specific problem of true (functional) delay estimation during high-level design. We present a method for modelling and verifying high-level timing specification using CLP (BNR), a constraint logic programming language augmented with relational interval arithmetic
Keywords
circuit analysis computing; delays; digital arithmetic; formal verification; high level synthesis; logic programming; timing; BNR; CLP; constraint logic programming; functional delay estimation; high-level design; high-level timing analysis; interval arithmetic; modelling; timing specification verification; Algorithm design and analysis; Analytical models; Arithmetic; Circuits; Computational modeling; Computer peripherals; Delay estimation; Logic programming; Performance analysis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1995. Canadian Conference on
Conference_Location
Montreal, Que.
ISSN
0840-7789
Print_ISBN
0-7803-2766-7
Type
conf
DOI
10.1109/CCECE.1995.526284
Filename
526284
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