Title :
High-level timing analysis using constraint logic programming and interval arithmetic
Author :
Girodias, Pierre ; Cerny, Eduard
Author_Institution :
Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
Abstract :
This paper addresses the specific problem of true (functional) delay estimation during high-level design. We present a method for modelling and verifying high-level timing specification using CLP (BNR), a constraint logic programming language augmented with relational interval arithmetic
Keywords :
circuit analysis computing; delays; digital arithmetic; formal verification; high level synthesis; logic programming; timing; BNR; CLP; constraint logic programming; functional delay estimation; high-level design; high-level timing analysis; interval arithmetic; modelling; timing specification verification; Algorithm design and analysis; Analytical models; Arithmetic; Circuits; Computational modeling; Computer peripherals; Delay estimation; Logic programming; Performance analysis; Timing;
Conference_Titel :
Electrical and Computer Engineering, 1995. Canadian Conference on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7803-2766-7
DOI :
10.1109/CCECE.1995.526284
