Memory-bandwidth performance of the sliding-window based routers/switches

The new class of sliding-window packet switch architecture can be used in Internet routers and gigabit Ethernet switches for internal movement of the packets from its input ports to the output ports. The class of sliding-window switch architecture allows port sharing of its entire memory resource that is comprised of physically separate and parallel memory-modules. However, there are instances where due to preoccupation of memory locations, the parallel storage of all packets belonging to an input cycle may not be possible in just one memory-cycle. This increases the memory-bandwidth requirement of the switching system. In this paper, we present two different memory assignment schemes and compare the performance in terms of memory-bandwidth requirement. It is observed that the parameter-i assignment schemes have direct impact on the memory-bandwidth requirement of the switch. For the parameter-i assignment, the assignment scheme-2 has improved the performance in terms of worst-case memory-bandwidth requirement compared to that of assignment scheme-1.