DocumentCode :
3484372
Title :
Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform
Author :
Richard, E. ; Fox, R. ; Monget, C. ; Zaleski, M. ; Ferreira, P. ; Guvenilir, A. ; Brun, P. ; Oilier, E. ; Guillermet, M. ; Mellier, M. ; Petitdidier, S. ; Delsol, R. ; Besling, W. ; Marinier, L. ; Imbert, G. ; Lagha, A. ; Broussous, L. ; Rasco, M. ; Cregu
Author_Institution :
NXP Semicond., Crolles
fYear :
2007
fDate :
12-14 June 2007
Firstpage :
178
Lastpage :
179
Abstract :
A full ULK (ultra low-k) integration using TFHM (trench first hard mask) architecture (Hinsiger et al., 2004) is demonstrated in a high density CMOS 45 nm device. 13 nm-pitch metal features have been resolved using a 193 nm immersion hyper-NA (numerical aperture) scanner and an optimized OPC (optical proximity correction) model. RC performance and yield results are presented for a fully-integrated 45 nm ULK backend. An overall speed performance enhancement of >10% has been confirmed within a microprocessor application at the 65 nm technology node when replacing Low-k dielectric (k=2.9) with ULK (k=2.5) material.
Keywords :
CMOS integrated circuits; CMOS Platform; TFHM; full ULK integration; hyper-NA scanner; microprocessor application; numerical aperture; optical proximity correction; optimized OPC model; size 130 nm; size 193 nm; size 45 nm; trench first hard mask; Bonding; Dielectric materials; Etching; Lithography; Manufacturing; Materials reliability; Microprocessors; Packaging; Performance gain; Resists;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
Type :
conf
DOI :
10.1109/VLSIT.2007.4339683
Filename :
4339683
Link To Document :
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