Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner

Author

Zhu, Huilong ; Yang, Daewon ; Kumar, Mahender ; Colt, John ; Maxson, Jeff ; Scholl, Fred ; Chen, Derek ; Leach, Deb ; Leobandung, Effendi

Author_Institution

IBM Semicond. R&D Center (SRDC), Hopewell Junction

fYear

2007

fDate

12-14 June 2007

Firstpage

180

Lastpage

181

Abstract

This paper presents a simple, effective, and economical method to improve the yield of high performance 65 nm SOI CMOS technology using dual stress nitride liner (DSL) for performance enhancement. Sputtering is used to reduce the complexity caused by DSL boundaries to smooth/trim the top surface of the DSL, which results into a significant yield increase. The perfect yield of 36 Mb 0.65 mum² SRAM is increased by 25%. The yield for dual-core microprocessors is increased by 33% and for single-core microprocessors by 75%. Yield improvement is explained and sputtering effects on DSL stress and device performance are discussed. This method is in qualification process for product manufacturing.

Keywords

CMOS integrated circuits; microprocessor chips; silicon-on-insulator; sputtering; SOI CMOS technology; SRAM; dual stress liner; dual-core microprocessors; sputtering; CMOS technology; DSL; Microprocessors; Principal component analysis; Random access memory; Research and development; Sputter etching; Sputtering; Stress; Surface topography;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339684

Filename

4339684