Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM

Author

Park, Y.K. ; Lee, S.-H. ; Lee, J.W. ; Lee, J.Y. ; Han, S.H. ; Lee, E.-C. ; Kim, S.Y. ; Han, J. ; Sung, J.H. ; Cho, Y.J. ; Jun, J.Y. ; Lee, D.J. ; Kim, K.H. ; Kim, D.K. ; Yang, S.C. ; Song, B.Y. ; Sung, Y.S. ; Byun, H.S. ; Yang, W.S. ; Lee, K.H. ; Park, S.

Author_Institution

Samsung Electron. Co., Kyungki

fYear

2007

fDate

12-14 June 2007

Firstpage

190

Lastpage

191

Abstract

A 56 nm feature sized 1 Gb DRAM technology is successfully developed using ArF immersion lithography with a novel integration scheme. The cell size is 0.019 mum, which is the smallest one ever reported. In order to achieve high performance transistor characteristics with scaled down channel length, gate electrode is changed with dual poly tungsten metal gate, as well as elevated source-drain area with selective epitaxial growth (SEG) Si layer. For the data retention of DRAM cell, Asymmetric channel doping (ASC) is more localized through the data node contact of the cell transistor. High aspect ratio OCS structure and ZAZ dielectric scheme were developed for high cell capacitance.

Keywords

DRAM chips; argon compounds; dielectric materials; electrodes; epitaxial growth; lithography; transistors; DRAM technology; asymmetric channel doping; dielectric scheme; dual poly tungsten metal gate; gate electrode; high cell capacitance; immersion lithography; integration scheme; memory size 1 GByte; selective epitaxial growth; size 56 nm; Capacitance; Doping; Electrodes; Electrostatic discharge; Immune system; Lithography; MOS devices; Random access memory; Tin; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339688

Filename

4339688