Author :
Chudzik, M. ; Doris, B. ; Mo, R. ; Sleight, J. ; Cartier, E. ; Dewan, C. ; Park, D. ; Bu, H. ; Natzle, W. ; Yan, W. ; Ouyang, C. ; Henson, K. ; Boyd, D. ; Callegari, S. ; Carter, R. ; Casarotto, D. ; Gribelyuk, M. ; Hargrove, M. ; He, W. ; Kim, Y. ; Linde
Abstract :
Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Ã…) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Ã… Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET´s fabricated with gate-first high thermal budget processing with thin Tinv (≪13Ã…) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET´s into CMOS devices yielded large SRAM arrays.
Keywords :
CMOS integrated circuits; field effect transistors; silicon-on-insulator; substrates; CMOS devices; SRAM arrays; dual stress liners; gate-first processing; high-kappa/metal gate nFET devices; short channel control; silicon-on-insulator substrates; size 45 nm; thermal budget processing; CMOS logic circuits; CMOS process; CMOS technology; Electronic components; Helium; Random access memory; Research and development; Silicon on insulator technology; Stress; Substrates;
