Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

We achieved 635/250 muA/mum @ I_off=20 pA/mum unstrained FuSI/HfSiON nMOS/pMOS devices (Vdd=1.1 V, I_off=20 pA/mum, J_g=20/8 mA/cm²) representing a 20%/2% device improvement enabling 10% power delay improvement compared to our previous report. This was reached by a careful optimization of the nitrogen content into our HfSiON gate dielectric (to be 3-6%). Second, we demonstrate that the nitrogen content impacts not only the device performance but also the gate leakage current, the gate oxide integrity as well as PBTI and NBTI. We also report for the first time a 0.8 nm EOT HfSiON dielectric with Ni-FuSI gate and its impact on ring oscillator delay resulting in 9 ps delays. This is an absolute record for any CMOS with metal gate to date.