Reconfigurable hardware acceleration for a cryptographically inspired pseudo-random sequence generation engine

This paper describes the design and implementation of an encryption based algorithm for random sequence generation on reconfigurable hardware. This engine is designed using a nonlinear bit-mixing function that is derived from the data encryption algorithm used in the data encryption standard (DES). By exploiting the parallel processing scheme that is inherent to field-programmable gate arrays (FPGAs) for hardware-based algorithmic acceleration, more efficient systems have been designed. The fastest hardware implementation is capable of processing the random sequence generation algorithm more than 40x faster than the conventional, microprocessor implementation.