Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration

Author

Uejima, K. ; Nakamura, H. ; Fukase, T. ; Mochizuki, S. ; Sugiyama, S. ; Hane, M.

Author_Institution

NEC Corp., Tokyo

fYear

2007

fDate

12-14 June 2007

Firstpage

220

Lastpage

221

Abstract

Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) are proposed, for the first time, demonstrating efficient stress-transfer from the dual stress liner (DSL) to the FET channel region. A thin L-shape sidewall formed by the DDSW process was designed to compensate decreased channel stress resulted from the aggressive pitch scaling. A +10% enhancement of channel conductance has been achieved for NTETs by the DDSW process compared with a conventional DSL one. For PFETs, achieved +23% I_on enhancement by using the ART, was resulted from avoiding stress degradation in the DSL process and optimizing the DSL layout.

Keywords

CMOS integrated circuits; field effect transistors; stress effects; FET channel region; NTET; adhesion reinforcement technique; aggressive pitch scaling; channel conductance; double disposable sidewall spacers process; dual stress liner CMOS integration; stress transfer; thin L-shape sidewall; Adhesives; CMOS process; CMOS technology; Compressive stress; DSL; Degradation; MOSFETs; Silicides; Subspace constraints; Tensile stress; DSL layout; disposable spacer and adhesion; dual stress liner; stress proximity; stress transfer;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339700

Filename

4339700