Title :
Impact of Layout, Interconnects and Variability on CMOS Technology Roadmap
Author :
Boeuf, Frederic ; Sellier, Manuel ; Farcy, Alexis ; Skotnicki, Thomas
Author_Institution :
STMicroelectronics, Crolles
Abstract :
In this paper, using the new generation of MASTAR software we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation and variability, such as loaded ring-oscillator delay as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%/year delay improvement to construct a new industrially viable roadmap.
Keywords :
CMOS integrated circuits; electronic engineering computing; 6T-SRAM functionality; CMOS technology roadmap; MASTAR software; circuit performance; loaded ring-oscillator delay; power dissipation; variability; CMOS logic circuits; CMOS technology; Capacitance; Circuit testing; Delay; Fluctuations; Integrated circuit interconnections; Logic devices; Logic testing; Power generation;
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
DOI :
10.1109/VLSIT.2007.4339712
