DocumentCode :
3485045
Title :
1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate
Author :
Sakoda, Tsunehisa ; Tamura, Naoyoshi ; Xiao, Shiqin ; Minakata, Hiroshi ; Morisaki, Yusuke ; Nishigaya, Keita ; Saiki, Takashi ; Uetake, Toshiyuki ; Iwasaki, Toshio ; Ehara, Hideo ; Matsuyama, Hideya ; Shimizu, Hiroshi ; Hashimoto, Koichi ; Kimoto, Masayo
Author_Institution :
Fujitsu Lab. Ltd., Tokyo
fYear :
2007
fDate :
12-14 June 2007
Firstpage :
26
Lastpage :
27
Abstract :
We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.
Keywords :
MOSFET; SRAM chips; probability; MOS transistors; circuit failure-rate; gate-current fluctuation probability; large-scale SRAM; quantitative failure-rate calculation; ultrathin gate-dielectric; Circuit simulation; Current measurement; Dielectric measurements; Fluctuations; Large-scale systems; MOS devices; Probability; Random access memory; Stress measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
Type :
conf
DOI :
10.1109/VLSIT.2007.4339713
Filename :
4339713
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3485045
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