Title :
A multiple domain environment for efficient simulation
Author :
Lentz, Karen P. ; Manolakos, Elias S. ; Czeck, Edward C.
Author_Institution :
Tufts Univ., Medford, MA, USA
Abstract :
The paper presents a concurrent simulation methodology for digital logic experimentation, which supports a multiple experiment environment for creating and maintaining scenarios of independent experiments without being exhaustive. It efficiently compresses multiple experiments in a single simulation and requires no pre-analysis of the circuit. In addition, scenarios can be created which allow experiments to interact with each other and spawn offspring experiments should new behaviors arise. The user initializes the simulation with independent experiments and the interactions are dynamically created if necessary. By utilizing the similarity among experiments, we gain efficiency in storage and CPU time without resorting to parallel hardware. Providing this capability in digital logic simulators, allows more test cases to be run in less time, provides the exact location and causes of every behavior and can be used to track the signature paths of test patterns for coverage analysis. We describe the multiple experiment algorithms, discuss the function list that makes dynamic interactions possible and report on its effectiveness for attacking an exhaustive simulation problem such as Multiple Stuck-at Fault simulations for digital logic. New directions for this type of testing methodology and applicability to other model types for creating experiment scenarios are also discussed based on our results
Keywords :
circuit analysis computing; logic CAD; logic testing; parallel programming; Multiple Stuck-at Fault simulations; concurrent simulation methodology; coverage analysis; digital logic; digital logic experimentation; digital logic simulators; dynamic interactions; efficient simulation; exhaustive simulation problem; function list; independent experiments; multiple domain environment; multiple experiment algorithms; multiple experiment environment; parallel hardware; signature paths; Aggregates; Analytical models; Availability; Circuit faults; Circuit simulation; Circuit testing; Hardware; Logic design; Logic testing; Pattern analysis;
Conference_Titel :
Simulation Symposium, 1997. Proceedings., 30th Annual
Conference_Location :
Atlanta, GA
Print_ISBN :
0-8186-7934-4
DOI :
10.1109/SIMSYM.1997.586490