Author :
Wang, J. ; Tateshita, Y. ; Yamakawa, S. ; Nagano, K. ; Hirano, T. ; Kikuchi, Y. ; Miyanami, Y. ; Yamaguchi, S. ; Tai, K. ; Yamamoto, R. ; Kanda, S. ; Kimura, T. ; Kugimiya, K. ; Tsukamoto, M. ; Wakabayashi, H. ; Tagawa, Y. ; Iwamoto, H. ; Ohno, T. ; Saito
Abstract :
Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.
Keywords :
Ge-Si alloys; power field effect transistors; SiGe; channel strain; channel-stress enhancement technology; damascene gate process; embedded stressor technique; gate-1st process; pFET; recessed channel; Annealing; Capacitive sensors; Compressive stress; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Ion implantation; Plasma applications; Plasma devices; Silicon germanium; channel stress; damascene gate; embedded SiGe; high-k/metal gate; mobility enhancement; recessed channel;
