DocumentCode
3485247
Title
Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process
Author
Li, Hongmei ; Jagannathan, Basanth ; Wang, Jing ; Su, Tai-Chi ; Sweeney, Susan ; Pekarik, John J. ; Shi, Yun ; Greenberg, David ; Jin, Zhenrong ; Groves, Robert ; Wagner, Lawrence ; Csutak, Sebastian
Author_Institution
IBM Syst. & Technol. Group, Burlington
fYear
2007
fDate
12-14 June 2007
Firstpage
56
Lastpage
57
Abstract
Power gain (fMAX) of 350 GHz and cut-off frequency (fT) of 280 GHz is demonstrated for 36 nm Lpoly devices in a 45 nm bulk CMOS process. A record fT of 350 GHz (intrinsic fT 425 GHz), without any loss of fMAX is seen in 28 nm Lpoly devices. Combination of advanced lithography and liner stress effect can be leveraged to further boost fT and fMAX by 14% with a relaxed pitch device. Comparison with 90 and 65 nm nodes illustrates the impact of scaling and parasitics.
Keywords
CMOS integrated circuits; RF performance; bulk CMOS process; cut-off frequency; frequency 350 GHz; liner stress effect; lithography; power gain; size 45 nm; CMOS process; CMOS technology; Data mining; Electrical resistance measurement; Gain measurement; Lithography; Parasitic capacitance; Radio frequency; Stress; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-03-1
Type
conf
DOI
10.1109/VLSIT.2007.4339725
Filename
4339725
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