An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems

This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true “system on a chip” solution