A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm

Author

Wei-Cheng Chen ; Rong-Jyi Yang ; Chia-Yu Yao ; Chao-chyun Chen

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

338

Lastpage

342

Abstract

This paper presents a wide-operating-range, all digital delay-locked loop (ADDLL) that possesses fast and anti-harmonic lock behavior using a novel fast-lock variable SAR (FVSAR) algorithm. The FVSAR algorithm provides an efficient search sequence for the length-control code of the delay line in the ADDLL. An 11-bit FVSAR ADDLL prototype was fabricated in the TSMC 0.18-μm CMOS process. The chip´s core area is 0.2 mm². With 1.6-V supply, the power consumption of the ADDLL chip is less than 10 mW. Compared with the conventional VSAR algorithm, the proposed FVSAR ADDLL reduces the lock time by at least 35% when the input clock frequency is between 66 MHz and 550 MHz.

Keywords

CMOS digital integrated circuits; clocks; delay lock loops; power consumption; search problems; ADDLL chip; FVSAR ADDLL prototype; FVSAR algorithm; TSMC CMOS process; all digital delay-locked loop; antiharmonic lock behavior; delay line; fast lock behavior; fast-lock variable SAR algorithm; input clock frequency; length-control code; power consumption; search sequence; wide-operating-range; wide-range all-digital delay-locked loop; Algorithm design and analysis; CMOS integrated circuits; Clocks; Prototypes; Signal processing algorithms; Time frequency analysis; Timing; Binary Search Algorithm; Clock Generators; Delay-locked Loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on

Conference_Location

New Taipei

Print_ISBN

978-1-4673-5083-9

Electronic_ISBN

978-1-4673-5081-5

Type

conf

DOI

10.1109/ISPACS.2012.6473507

Filename

6473507