Circuit synthesis based on VHDL language transformations

One of the major problems within the VHDL based system synthesis is to start the design on a higher abstraction level than the register transfer level (RT-level). We present a novel synthesis procedure called SYLANT (Synthesis based on Language Transformations), which uses the methodology of high level synthesis. It starts from the abstract high-level functional model and produces an RT-level description through successive language transformations. The major advantage of this method is that neither a data-flow graph, nor any meta-language as internal representation is used, only the standard VHDL, This internal VHDL representation is accessible to the designer, and the circuit model can be simulated after each step during the synthesis flow. Different algorithms can be implemented for any step, and depending on the applied technology dependent information, various RT-level architectures can be obtained. The output VHDL format is suitable for continuing the design flow with RT-level based synthesis tools