Author :
Harris, H. Rusty ; Kalra, Pankaj ; Majhi, Prashant ; Hussain, Muhammed ; Kelly, David ; Oh, Jungwoo ; He, Dawei ; Smith, Casey ; Barnett, Joel ; Kirsch, Paul D. ; Gebara, Gabriel ; Jur, Jess ; Lichtenwalner, Daniel ; Lubow, Abigail ; Ma, T.P. ; Sung, Guan
Abstract :
Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.
Keywords :
CMOS integrated circuits; MOS integrated circuits; annealing; silicon compounds; DIBL; GIDL; NMOS; SiGe; dual channel CMOS integration; high k PMOS devices; size 32 nm; size 80 nm; standard activation anneal temperature; threshold voltage; Annealing; Capacitive sensors; Germanium silicon alloys; MOS devices; Photonic band gap; Silicon germanium; Strain control; Threshold voltage; Uniaxial strain; Very large scale integration;
