Silicon realization of an OFDM synchronization algorithm

Author

Johansson, Stefan ; Landström, Daniel ; Nilsson, Peter

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

Volume

1

fYear

1999

fDate

1999

Firstpage

319

Abstract

In this paper a hardware architecture for an OFDM synchronizer is presented. The proposed synchronization unit can be used in any OFDM system that uses a cyclic prefix. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where both time and frequency offset are estimated simultaneously. The synchronization unit also performs frequency correction, which means that no feedback to the analog parts is necessary. Although the algorithm is too complex to be implemented on today´s most powerful standard DSP, a hardware architecture that is optimized for the algorithm can be implemented with moderate complexity. The unit contains 32 kbit RAM and 5000 gates and the sample rate is 25 Msamples/s

Keywords

CMOS digital integrated circuits; OFDM modulation; application specific integrated circuits; correlators; data communication equipment; digital arithmetic; digital radio; digital signal processing chips; high-speed integrated circuits; silicon; synchronisation; telecommunication computing; 0.35 micron; 25 MHz; 32 kbit; CMOS process; CORDIC unit; DSP; OFDM synchronization algorithm; Si; Si ASIC realization; correlation; cyclic prefix; frequency correction; frequency offset; hardware architecture; orthogonal FDM synchronizer; time offset; Circuit synthesis; Delay; Digital signal processing; Digital video broadcasting; Frequency estimation; Frequency synchronization; Hardware; OFDM modulation; Signal generators; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812287

Filename

812287