Title :
A hybrid approach to design error detection and correction [VLSI digital circuits]
Author :
Veneris, Andreas ; Hajj, Ibrahim N.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for diagnosis and employs BDDs during correction so that it remains both computational efficient and accurate. Experimental results on ISCAS´85 benchmark circuits show that our approach can typically detect and correct 2 and 3 errors within seconds of CPU time
Keywords :
VLSI; circuit CAD; digital integrated circuits; error correction; error detection; integrated circuit design; logic CAD; BDD; VLSI circuit design; hybrid approach; logic design errors; logic error correction; logic error detection; multiple error correction; multiple error diagnosis; test vector simulation; Boolean functions; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Data structures; Design methodology; Error correction; Logic design; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812294
