• DocumentCode
    3486144
  • Title

    J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

  • Author

    Odanaka ; Rios, Rafael ; Kumashiro, S. ; Bhavnagarwala, A. ; Hane, M. ; Zhang, Kai ; Masuda, Hiroji ; Lee, Sang-Won ; Radens, Carl ; Amerasekera, A. ; Farrell, Jay A. ; Yoshimura, Hiroyuki

  • Author_Institution
    Osaka University
  • fYear
    2007
  • fDate
    12-14 June 2007
  • Firstpage
    150
  • Lastpage
    150
  • Keywords
    Crosstalk; Design for manufacture; Design methodology; Etching; Instruments; Large scale integration; National electric code; Predictive models; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-4-900784-03-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2007.4339771
  • Filename
    4339771
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3486144