DocumentCode :
3486202
Title :
Boolean factoring and decomposition of logic networks
Author :
Mishchenko, Alan ; Brayton, Robert ; Chatterjee, Satrajit
Author_Institution :
Dept. of EECS, Univ. of California, Berkeley, CA
fYear :
2008
fDate :
10-13 Nov. 2008
Firstpage :
38
Lastpage :
44
Abstract :
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs so that fast truth table manipulations can be used in all operations. Boolean methods lessen the structural bias of algebraic methods, while still allowing for high speed and multiple iterations. Experimental results on K-LUT networks show an average additional reduction of 5.4% in LUT count, while preserving delay, compared to heavily optimized versions of the same networks.
Keywords :
Boolean functions; logic circuits; matrix decomposition; table lookup; Boolean factoring; K-LUT networks; disjoint-support decompositions; local transformations; logic networks; Boolean functions; Computer networks; Inverters; Joining processes; Logic circuits; Logic design; Logic functions; Logic gates; Table lookup; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-4244-2819-9
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2008.4681549
Filename :
4681549
Link To Document :
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