Title :
A performance comparison of several superscalar processor models with a VLIW processor
Author :
Lenell, John ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
This paper quantitatively compares various superscalar processor architectures with a very long instruction word architecture developed at the University of California, Irvine. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each
Keywords :
instruction sets; parallel architectures; performance evaluation; VLIW processor; dynamically scheduled processor; hardware resources; performance comparison; processor architectures; statically scheduled processor; superscalar processor models; very long instruction word architecture; Computer architecture; Decoding; Dynamic scheduling; Hardware; Hazards; Optimizing compilers; Out of order; Parallel processing; Processor scheduling; VLIW;
Conference_Titel :
Parallel Processing Symposium, 1993., Proceedings of Seventh International
Conference_Location :
Newport, CA
Print_ISBN :
0-8186-3442-1
DOI :
10.1109/IPPS.1993.262853
