DocumentCode
3486676
Title
The effect of wells on gate oxide charging during plasma processing
Author
Linder, Barry P. ; En, William G. ; Cheung, Nathan W.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1996
fDate
16-21 Jun 1996
Firstpage
788
Lastpage
791
Abstract
The effect of wells and substrate type on gate oxide charging during Plasma Immersion Ion Implantation is modeled. The simulation combines the equations governing the plasma currents and integrated circuit device models to determine the gate oxide stressing voltage during implantation. Depending on the substrate type and the surface potential (Vs), a depletion region may exist, reducing the gate oxide voltage, and hence the gate oxide damage. This occurs for a P-substrate with a positive Vs and for an N-substrate with a negative Vs. Well structures by the nature of their capacitance, modulate Vs, altering the oxide stressing voltage. P-wells result in a more positive Vox, while N-wells result in a more negative Vox. Experimental results confirm the substrate effect, while they are inconclusive on the effect of wells. Including both the substrate and well effects results in a more complete picture of oxide charging
Keywords
ion implantation; semiconductor process modelling; N-substrate; P-substrate; damage; depletion region; gate oxide charging; integrated circuit device model; plasma current; plasma immersion ion implantation; simulation; stressing voltage; surface potential; well; Capacitance; Circuit simulation; Equations; Integrated circuit modeling; Plasma devices; Plasma immersion ion implantation; Plasma materials processing; Plasma simulation; Surface charging; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Ion Implantation Technology. Proceedings of the 11th International Conference on
Conference_Location
Austin, TX
Print_ISBN
0-7803-3289-X
Type
conf
DOI
10.1109/IIT.1996.586575
Filename
586575
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